On software implementation of Kuznyechik on Intel CPUs

Fast Sort on CPUs, GPUs and Intel MIC Architectures

Theoretical Peak FLOPS per instruction set on modern Intel CPUs

It used to be that evaluating the theoretical peak performance of a CPU in FLOPS (floating point operations per seconds) was merely a matter of multiplying the frequency by the number of floating-point instructions per cycles. Today however, CPUs have features such as vectorization, fused multiply-add, hyper-threading or “turbo” mode. In this paper, we look into this theoretical peak for recent...

Efficient Implementation of XPath Processor on Multi-Core CPUs

Current XPath processors use direct approach to query evaluation which is quite inefficient in some cases and usually implemented serially. This may be a problem in case of processing complex queries on large documents. We propose algorithms and XML indexing techniques which are more efficient and which can utilize standard parallel templates. Our implementation is highly scalable and outperfor...

SSE Implementation of Multivariate PKCs on Modern x86 CPUs

Multivariate Public Key Cryptosystems (MPKCs) are often touted as future-proofing against Quantum Computers. It also has been known for efficiency compared to “traditional” alternatives. However, this advantage seems to erode with the increase of arithmetic resources in modern CPUs and improved algorithms, especially with respect to Elliptic Curve Cryptography (ECC). In this paper, we show that...

Scalability of a Kalman filter based track fit on Intel many-core CPUs

H. Bjerke1, S. Gorbunov2, I. Kisel∗2,3, V. Lindenstruth2, P. Post4, and R. Ratering4 1CERN, Geneva, Switzerland; 2KIP, University of Heidelberg, Germany; 3GSI, Darmstadt, Germany; 4Intel, Cologne, Germany As a result of increasing density of transistors and heat and power constraints, computers increasingly implement parallelism in hardware in order to speedup computation. This has manifested i...